A. Field of the Invention
The present invention relates generally to data processing systems and, more particularly, to systems and methods for detecting a memory read response latency in data processing systems.
B. Description of Related Art
Many conventional data processing systems require the use of random access memories (RAMs) for storing data essential for system functionality. Such systems include network devices, such as routers or bridges, in which essential routing data may be maintained in RAM devices. In systems employing certain types of RAMs, variations in the delay of the read response data from the RAMs may be substantial. The read response delay may depend on the particular RAM used in the data processing system. The read response delay represents the period between a data request to a RAM and the time at which the data propagates from the RAM to be received at the requesting circuitry. In some data processing systems, the RAM may generate a return clock (e.g., to clock the requested data into a requesting device/system) based on an input clock received from the data requesting device that includes a significant amount of skew relative to the input clock. This “clock skew” further induces a delay between a data read request and the time at which the data can be received, clocked, and read at the data requesting device or system. These delay variations may be due to a number of causes, including delay induced by on-chip gates and delay induced by printed circuit board (PCB) wires. The read response delay may further vary from circuit board to circuit board and even can vary between different RAMs on the same circuit board.
Conventionally, read response latency has been accounted for by assuming a worst case delay and synchronizing the read circuitry accordingly. Thus, during a RAM data read process in which less delay than the worst case exists, an unnecessary delay is introduced into the read process beyond what is necessary to read the data from memory. This unnecessary delay, when multiplied by numerous data reads, hinders the maximum read access capability of the data processing system and, thus, limits the quantity of data retrievable from RAM over any given period of time.
Therefore, there exists a need for systems and methods in data processing systems that can improve the read access capability of the data processing systems and, thereby, increase the quantity of data that can be retrieved from RAM during a given period.